Processes which implement lightly doped drain (LDD) structures are well known. Accordingly, reasons for using and advantages of the lightly doped drain structure are well documented. The conventional LDD process involves formation of gate sidewall spacers. A lightly doped drain region is typically implanted into a substrate prior to the formation of a sidewall spacer. The sidewall spacer is commonly formed by depositing a dielectric after the gate is formed and anisotropically etching the dielectric to create the spacer. With the sidewall spacer is place, a heavy source/drain dopant is implanted with the gate and sidewall spacer acting as a mask to provide source and drain regions laterally displaced from the gate edges by the width of the sidewall spacer. The process just detailed typically requires two or more photolithographic masking steps. When photolithographic masking steps are minimized, substantial manufacturing cost savings may be realized.
A control problem typically exists in the formation of sidewall spacers by anisotropic etching. A common dielectric material which is used for sidewall spacer formation is low temperature oxide (LTO). Due to variations in the etch and the lack of precise control in the etchback process, variations in the size of the sidewall spacers are common. In addition, damage to the edge of the gate oxide may occur during the etching reaction. The net result is that transistors with varying device characteristics may result as well as defective or inoperative transistors.
An additional problem associated with the gate oxide integrity can result from the heavy source and drain implantation step. Electrical charges created by the source and drain implant can create a large electric field across the gate oxide and possibly result in gate oxide failure and premature breakdown.